The present invention relates to a semiconductor integrated circuit device, and more particularly to the semiconductor integrated circuit device which may be operated at both high speed and low electric power.
In order to improve the performance of the semiconductor integrated circuit device composed of a CMOS circuit, some methods have been proposed such as shrinkage of a MOS transistor that is a component of the CMOS circuit, lowering of an absolute value of a threshold voltage of the MOS transistor, and raising of a supply voltage. In actual, however, with improvement of an operating speed of the CMOS circuit, the power consumption is increased accordingly. For example, as the threshold voltage of the MOS transistor is made lower and lower, the operating speed becomes higher and higher though the leak current is also increased. Likewise, with enhancement of the supply voltage, the operating speed is improved and but the operation power is increased as well. The increase of the power consumption gives rise to disadvantages of degrading the circuit performance and bringing about an erroneous operation. The heat caused by the increase of the power consumption has the adverse effect on the mount of the semiconductor integrated circuit devices, which disadvantageously leads to enhancing the manufacturing cost. Therefore, faster operation and the lower power consumption have been significant issues to improving the performance of the CMOS circuit.
As a method of overcoming these disadvantages, for example, reference may be given to the technique disclosed in 2000 International Solid-State Circuits Conference Digest of Technical Papers, pp.294-295 (February, 2000). This technique is arranged so that a processor that is operated at high speed and low electric power may be realized by controlling the operating clock frequency and the supply voltage of a microprocessor composed of a CMOS circuit. If the fast operation is required, by enhancing the clock frequency and the supply voltage, the operating speed may be improved as making the power consumption larger. On the other hand, if the slow operation is allowed, by lowering the clock frequency and the supply voltage, the power consumption may be reduced. The combinational adjustment of these controls through the operating system realizes the fast operation and the low power consumption of the microprocessor.
In order to realize the semiconductor integrated circuit device composed of a CMOS circuit such as a microprocessor that is operated at high speed and low electric power, the foregoing technique of controlling the operating clock frequency and the supply voltage of the CMOS circuit is an effective means. This technique makes it possible to speed up the clock frequency and enhance the supply voltage when the microprocessor operates at high speed and on the contrary to lower the clock frequency and the supply voltage when it operates at low electric power or low speed, thereby improving the performance of the microprocessor.
In recent days, the MOS transistor is shrunken more and more. As a result, the dimensions and performances of the transistors in the manufacturing process are made greatly variable. FIG. 3 shows dependency of a supply voltage on an operating frequency of a CMOS circuit. In FIG. 3, an axis of abscissa denotes a supply voltage and an axis of ordinates denotes an operating frequency. As shown, mainly because of the variations in the performance of the transistor, the operating frequency of the CMOS circuit varies in the range of the highest (best) speed, the standard (typical) speed and the low (worst) speed at the same supply voltage. If the CMOS circuit having such variations in an operating speed is used for composing the semiconductor integrated circuit device such as a microprocessor, the operating speed guaranteed to the device is determined to be the worst speed. As shown, as the supply voltage is made lower, the operation of the CMOS circuit is made slower accordingly. In the worst speed, the degrade of the operating speed is quite conspicuous, which is an obstacle to the performance of the microprocessor.
The possible suppression of the variations in the operating characteristic in the CMOS circuit leads to guaranteeing the typical speed as shown in FIG. 3. This results in making the CMOS circuit far faster in operation and lower in power consumption. The variations can be realized by controlling the substrate bias of the MOS transistor.
It is a first object of the present invention to provide a semiconductor integrated circuit device which is arranged to suppress the characteristic variations of the CMOS circuit and thereby to improve the circuit performance.
It is a second object of the present invention to provide a semiconductor integrated circuit device which may be operated at low electric power and is suitable especially to a portable instrument operated by a built-in battery without degrading the operating speed.
It is a third object of the present invention to provide a semiconductor integrated circuit device which may be operated at high speed without having to increase the power consumption.
It is a fourth object of the present invention to provide a system having the above-mentioned semiconductor integrated circuit mounted thereon which may be battery-operated for a longer length of time.
In carrying out the foregoing objects, the present invention offers the following concrete arrangements.
A semiconductor integrated circuit device includes a main circuit composed of at least one MOS transistor, a clock frequency controlling circuit for controlling a frequency of a clock signal to be supplied to the main circuit, a power voltage controlling circuit for controlling a supply voltage to be supplied to the main circuit, and a substrate bias controlling circuit for controlling a substrate bias to be supplied to a well where the MOS transistor of the main circuit is formed, wherein the semiconductor integrated circuit device controls a frequency of a clock signal, a value of a supply voltage and a value of the substrate bias according to the operating performance to be requested by the main circuit.
The limit value of the consumed power that is one parameter of the operating performance is changed according to the remaining quantity of the battery power for feeding the device. If the remaining quantity is smaller, the consumed power is reduced, so that the life of the battery is extended.
In addition, a command signal generated by a command generating circuit may be determined on a command to be sent from the operating system, a command to be sent from an application software, a signal to be inputted from the external to the semiconductor integrated circuit device, a signal to be sent from a memory such as ROM or FLASH, or an amount of load to be processed by the main circuit.
The main circuit is divided into two or more blocks, in each of which blocks the clock frequency, the supply voltage and the substrate bias are controlled so that the most approximate performance may be achieved. This makes it possible for the main circuit to operate on the operating characteristics according to the processing load to be done by each block, for realizing more minute control.
Further, the system arranged to use the foregoing semiconductor integrated circuit device is disclosed. In the system including the semiconductor integrated circuit device, the battery, and the voltage converting circuit, the semiconductor integrated circuit device is supplied with the electric power from the battery through the voltage converter. According to the present invention, a switch is provided so that the electric power from the battery may be directly supplied to the semiconductor integrated circuit device without passing through the voltage converter. If the quantity of the remaining power of the battery is made smaller, the device is fed directly from the battery without passing through the voltage converter by operating the switch. In this feeding, the voltage converter is not required, which leads to extending the battery life.